The approaches described in this background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not known to be prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
An analog to digital converter (ADC) is an electronic system, circuit, or a module that converts analog input signals to digital code words. The industry-accepted basis for testing ADCs is a comparison of a known count of each of the digital code words for an ideal ADC for a given input to the actual count of each of the digital code words of a device under test. An ideal ADC is a theoretical concept, and cannot be implemented in real life. It has infinite resolution, where every possible analog input signal gives a unique digital code word from the ADC within the specified conversion range.
A common method of testing an ADC device under test employs a histogram whereby a tester signal composed of a series of analog signals from a tester site is applied to the ADC, which converts the series of analog signals to a series of digital code words. The series of digital code words are recorded in memory relating to each voltage level applied at the input. The tester signal is designed so that it has a known probability density function (PDF) of expected values of the series of digital code words.
A typical ADC test setup includes different hardware units such as a signal generator, a clock generator, a system or device for data acquisition (for example an interface to a personal computer (PC) data-acquisition (DAQ) card or a printer port) and logic for data analysis. The signal generator, which may be an arbitrary waveform generator, is used to provide the test signal to the ADC. A clock generator synchronizes the conversion process and transfers the output series of digital code words to the logic for data analysis through the data acquisition device. The data analysis logic builds a histogram by storing the values of each digital code word in the series of digital code words in appropriate histogram bins wherein the histogram bins are storage locations in a memory. The data analysis logic then analyses the histogram data and determines whether the ADC passed the testing.
The ADC test setup described above has several problems. This setup is distributed with the ADC being formed on a separate device from the data acquisition device and the data analysis logic. This setup is also costly and of limited use since it serves a singular purpose of ADC testing. The typical ADC testing system does not have the capability to automatically change the digital words directly into histogram. The typical system makes use of a personal computer to keep all digital words in storage and to handle and change the digital data into a histogram format before performing the analysis to identify a pass/fail result. Furthermore, analysis of the histogram data requires large volume of sampled data and consequently large storage space to be reserved at runtime. For example, a 12-bit ADC can generate 212 (or 4096) distinct code words. Assuming every digital code word must be digitized once, the system needs to allocate 4096 memory spaces to store the 12-bit digital value for each digital code word, totaling 4096 times 12 bits. In a typical test setup, each of the digital code words is repeated at least 500 times in order to meet the required sample size for different statistical analysis. Therefore, the test setup needs to preserve at least 500 times 4096 times 12 bits (24 Megabits) of storage space during runtime for testing an ADC. Thus, there exists a need for an on-chip histogram testing solution that requires less storage space during runtime.